1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to an integrated circuit having an electrostatic discharge (ESD) protection circuit, where the integrated circuit utilizes a bipolar transistor and substrate triggering technique to improve/enhance ESD protection ability.
2. Description of the Prior Art
In advanced semiconductor manufacturing processes, a multi-functions circuit can be integrated into a single chip, in which a conducting pad on the chip is utilized for receiving an external voltage source (e.g., a bias source) or for exchanging data with other external circuits/chips. For example, the power pads installed on the chip is utilized for receiving bias voltages, i.e., the VDD node and VSS node. Furthermore, the signal pad, i.e., I/O pad, installed on the chip is utilized for receiving an input signal and/or an output signal.
In this way, the chip communicates with other circuits/chips through the above-mentioned conducting pads. The electro static signal, however, may be transmitted into the chip through the pads of the chip during the processes of manufacturing, packaging, testing, or shipping, and damage the internal circuit of the chip. Thus, in advanced semiconductor integrated circuits, an electro-static discharge (ESD) circuit is an important element utilized for protecting the internal circuit from being damaged by the electro static signal.
Conventionally, the ESD circuit is installed between every two pads of the chip. When the electro static signal occurs in the chip, the ESD circuit conducts a low resistance current path between the two pads for bypassing the current induced by the electro static signal, thereby preventing the current from flowing into the internal circuit of the chip. Accordingly, the internal circuit of the chip can be protected by the ESD circuit.
The ability of the ESD circuit to discharge the electro static signal can be tested through the following modes: positive to VSS (PS) mode, negative to VSS (NS) mode, positive to VDD (PD) mode, negative to VDD (ND) mode, and inter-power mode (e.g., VDD to VSS (DS) mode). For the example of the PS mode, when the chip is tested under the PS mode, the pad connected to the VSS is connected to ground, and a positive electro static signal is generated at the pad under test of the chip for turning on the ESD circuit to discharge the electro static signal into the pad connected to the VSS. Meanwhile, the pad connected to the VDD and the other pads are floating. When the chip is tested under the ND mode, the pad connected to the VDD is connected to ground, and a negative electro static signal is generated at the pad under test of the chip for turning on the ESD circuit to discharge the electro static signal into the pad connected to the VDD. Meanwhile, the pad connected to the VSS and the other pads are floating.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional electro-static discharge (ESD) integrated circuit 100. The integrated circuit 100 comprises a first power pad 101, a second power pad 102, a signal pad 103, a resistive element 105, an internal circuit 110, two diodes 121, 122, and a power clamp circuit 130, wherein the power clamp circuit 130 comprises a gate-grounded N type metal oxide semiconductor (MOS) transistor 132 and a gate-powered P type MOS transistor 134. In FIG. 1, the first power pad 101 is connected to the VDD node, and the second power pad 102 is connected to the VSS node. Conventionally, the power clamp circuit 130 can also be implemented by only the gate-grounded N type MOS transistor 132 or only the gate-powered P type MOS transistor 134.
Please refer to FIG. 1 again. The diode 121 is configured as the ESD protection circuit between the signal pad 103 and the first power pad 101, and the diode 122 is configured as the ESD protection circuit between the signal pad 103 and the first power pad 102. Furthermore, the above-mentioned power clamp circuit 130 is configured as the ESD protection circuit between the first power pad 101 (i.e., VDD) and the second power pad 102 (i.e., VSS).
When enlarging the size of the N type MOS transistor 132 or the P type MOS transistor 134, the ability to discharge the electro static signal may not improve accordingly since the N type MOS transistor 132 and the P type MOS transistor 134 do not turn on concurrently. Therefore, a novel ESD protection mechanism should be introduced to solve the above-mentioned problem.